Amit Sharma, Synopsys
Typically, fields and registers are assumed to be implemented in individual, dedicated hardware structures with a constant and permanent physical location such as a set of D flip-flops. However for some registers which are typically large in number, implementing them in memory or RAM instead of individual flip-flops is most efficient. These are the virtual fields and virtual registers, and as they are implemented in a RAM, their physical location and layout is created by an agreement between the hardware and the software, not by their physical implementation.
Virtual fields and registers can be modeled using RAL by creating a logical overlay on a RAL memory model that can be accessed as if they were real physical fields and registers. Virtual fields are contained in virtual registers.
Virtual registers are defined as continuous locations within a memory and can span across multiple memory locations. They are always composed of entire memory locations and not fractions and are modeled arrays associated with a memory.
The association of a virtual register array with a memory can be static or dynamic, but the structure of these registers should be specified in the RALF file.
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Static virtual registers are associated with a specific memory and are located at specific offsets within this memory. This association should be specified in the RALF file as shown in the following example. This association is permanent and cannot be broken at runtime.
Static Virtual Register Array:
Example 1 :
memory ram1 { size 32; bits 8; access rw; initial 0; }
block dut { bytes 2; memory ram1@0×0000 virtual register vreg[3] ram1 @0×5 +2 { bytes 2; field f1 { bits 4; }; field f2 { bits 4; }; field f3 { bits 8; }; } }
An array of new virtual registers with array size as 3 is associated with the memory ‘ram1′ starting at the offset 5. The increment value is specified as 2 as minimum 2 locations in the memory are required to implement 1 virtual register. The 3 virtual registers are associated with the ram1 as shown:
vreg[0] is associated at offset 0×5 of ram1. vreg[1] is associated at offset 0×7(0×5 +2) of ram1. vreg[2] is associated at offset 0×9(0×7 +2) of ram1. vreg2[2] is associated at offset 0×24(0×22 +2) of ram1.
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Dynamic virtual registers are associated with a user-specified memory and are located at user-specified offsets within that memory. The association is done at runtime. The dynamic allocation of virtual register arrays can also be performed randomly by a Memory Allocation Manager instance.
The number of virtual registers in the array and its association with the memory is specified in the SystemVerilog code and must be correctly implemented by the user. Dynamic virtual registers arrays can be relocated or resized at runtime.
Dynamic Virtual Register Array:
Example 1:
memory ram1 { size 64; bits 8; access rw; initial 0; }
virtual register vreg { bytes 2; field f1 { bits 4; }; field f2 { bits 4; }; field f3 { bits 8; }; }
block dut { bytes 2; memory ram1@0×0000 virtual register vreg=vreg1; virtual register vreg=vreg2; }
Here, the virtual register structure is specified in the RALF file, but the association is done during runtime (in the env or testcase) in one of the following ways:
a. Dynamic specification:
env.ral_model.vreg1.implement(4,env.ral_model.ram1,’h20,2);
Virtual register array of size 4 is implemented starting at the offset ‘h20 of the memory ram1 and ‘2′ is the increment value. The virtual registers will be associated as:
vreg1[0] is associated at offset 0×20 of ram1. vreg1[1] is associated at offset 0×22(0×20 +2) of ram1. vreg1[2] is associated at offset 0×24(0×22 +2) of ram1. vreg1[3] is associated at offset 0×26(0×24 +2) of ram1.
b. Randomly implemented dynamic specification:
env.ral_model.dut.vreg2.allocate(5,env.ral_model.dut.ram1.mam);
Virtual register array of size 5 is allocated randomly by the memory allocation manager (MAM). The allocated region is randomly selected in the address space managed by the specified MAM.
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Hope this post would help you to model and verify the registers and fields implemented in the DUT more efficiently. Please look out for the next blog post where I will talk about the different modes through which you can access these registers and fields
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