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Accessing Virtual Registers in RAL

Accessing Virtual Registers in RAL
Posted on Thursday, August 5, 2010 - 00:08 by Amit Sharma from the site Verification Martial Arts
Amit Sharma, Synopsys In one of my previous posts on  Virtual Registers I talked about how you use RAL to model Virtual Registers or fields which are an efficient means of implementing large number of registers in  memory or RAM instead of individual flip-flops.  I also mentioned that they are  implemented as arrays associated with a memory. In this post, I will talk about how you access these registers through RAL. Normal registers can be accessed using  the hierarchical name in RAL. For these, RAL  would generate the offsets and addresses required.  However, for virtual registers, along with  the virtual register name you need to provide the index ID to refer to them for read and write operations. Accordingly, RAL  generates the offset address based on the index ID of the virtual register. Consider the following example: The above RALF specification would translate into the following SV classes in the RAL model   ‘DMA_BFRS’  which is the instance of the Virtual Registers class ‘ral_vreg_dut_DMA_BFRS’ is not an array in the RAL Model and is thus different from a typical register array modeled in RAL. Now, how do you access the individual registers mapped to the memory?  You have to specify the index as the argument to the read/write methods. For example, To access the 4th index of this array, the access would like: blk.DMA_BFRS.write(4, status, ‘hFF); RAL would ultimately access the RAM to enable this access. Hence, the following are functionally equivalent: blk.DMA_BFRS.write(4, status, ‘hFF); and blk.ram.write(4 * 0×0004 + 0×1000, status, ‘hFF); The following illustration explains this point: You can see that you now have an option to access these registers in different modes, but both will eventually go through the RAM. You can leverage the Virtual register Callbacks or the RAL memory callbacks for additional customizations and extensibility, in addition to other capabilities that you get when you are using VMM RAL. Hope, this was useful.. do comment on any other specific functionality that you might look at when modeling these kind of registers.
Amit Sharma
Amit Sharma, Synopsys In one of my previous posts on  Virtual Registers I talked about how you use RAL to model Virtual Registers or fields which are an efficient means of implementing large number of registers in  memory or RAM instead of individual flip-flops.  I also mentioned that they are  implemented as arrays associated with a memory. In this post, I will talk about how you access these registers through RAL. Normal registers can be accessed using  the hierarchical name in RAL. For these, RAL  would generate the offsets and addresses required.  However, for virtual registers, along with  the virtual register name you need to provide the index ID to refer to them for read and write operations. Accordingly, RAL  generates the offset address based on the index ID of the virtual register. Consider the following example: The above RALF specification would translate into the following SV classes in the RAL model   ‘DMA_BFRS’  which is the instance of the Virtual Registers class ‘ral_vreg_dut_DMA_BFRS’ is not an array in the RAL Model and is thus different from a typical register array modeled in RAL. Now, how do you access the individual registers mapped to the memory?  You have to specify the index as the argument to the read/write methods. For example, To access the 4th index of this array, the access would like: blk.DMA_BFRS.write(4, status, ‘hFF); RAL would ultimately access the RAM to enable this access. Hence, the following are functionally equivalent: blk.DMA_BFRS.write(4, status, ‘hFF); and blk.ram.write(4 * 0×0004 + 0×1000, status, ‘hFF); The following illustration explains this point: You can see that you now have an option to access these registers in different modes, but both will eventually go through the RAM. You can leverage the Virtual register Callbacks or the RAL memory callbacks for additional customizations and extensibility, in addition to other capabilities that you get when you are using VMM RAL. Hope, this was useful.. do comment on any other specific functionality that you might look at when modeling these kind of registers.
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