Requirements-driven declarative verification
The Hyper Analytix solution for RTL verification is a standards-based requirements-driven declarative verification platform that enables you to automate a large portion of the verification process. With it, you can eliminate procedural test benches from your all or part of your environment. The figure below shows a high level view of how the solution fits in a hierarchical verification flow.
In comparison to the corresponding diagram for traditional verification methodologies, you can see that test benches are removed. Instead, you simply declare the requirements that you wish to verify using standard Verilog, VHDL, or SystemVerilog and declare a set of coverage goals (i.e. a coverage model) that you want to see satisfied. The tool does the rest.
You can apply requirements-driven declarative verification to any block in your verification process from the smallest module to full chip. The requirements for a given block include two parts:
- A declarative description of the environment in which the block resides
- A declarative description of the functionality of the block. That is, how the block should respond to stimulus provided by the environment
We leverage verification engineers’ well-understood notion of coverage, but apply it in a completely novel way to improve verification quality and to provide metrics that verification engineers, designers, and managers can use to assess verification confidence. The coverage model is specified in the context of each individual requirement so that coverage hits are recorded only when they are relevant to the requirement being verified. Coverage hits that are not relevant to the requirement being verified are not recorded. This ensures that the resulting coverage report does not contain false positives.
Software tools
The RTL verification solution consists of two key tools:
- A requirements-driven Verification Automation Environment called HyperVAE
- A server-based multi-threaded verification engine called HyperVerifier
The concept of a truly executable verification plan is the basis for HyperVAE. A verification plan in HyperVAE is a hierarchical breakdown of features to test and encapsulates the following elements:
- Specific requirements for each feature
- How to quantitatively measure verification confidence for each feature (i.e. coverage model)
Because the executable plan drives the verification process, it is very important for users to create well-defined, consistent plans. To support this activity, HyperVAE contains several methodology wizards, which use embedded domain knowledge to assist and guide users in the process of creating good verification plans. HyperVEE also has a metric wizard, which analyzes the RTL and uses the results of this analysis to assist in the process of creating quantitative verification metrics.
Once the plan is in place and the design ready, HyperVAE sends all or part of the plan to HyperVerifier. HyperVerifier manages all available compute power to systematically analyze the design to determine whether the design meets the stated requirements. During this analysis, HyperVerifier will either find bugs or it will return an actionable set of metrics that indicate the confidence level of the verification process that HyperVerifier performed. For any bugs found, HyperVerifier returns simulation traces showing how to stimulate these bugs.
More details
The tools mentioned above are still in development and we are not yet ready to disclose more details at this time. If you would like to be notified when more information and/or demonstrations become available, please contact us using the Contact menu above or by clicking here.
We also encourage you to register on this website and subscribe to our newsletter or subscribe to our announcements RSS feed.