RAL

Adiel Khan, Synopsys CAE Increasingly, more design-oriented engineers are writing VMM code. Some are trying to map typically good design architecture practices to verification development. A dangerous mapping is parameterization, from modules to classes. In my old Verilog testbenches I would develop reusable modules and use #parameters extensively to control the settings of the modules I was instantiating. (It was a sad day when I heard IEEE was deprecating my friend the defparam). 1.