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Low Power Techniques

Multi Threshold (MVT) Voltage Technique
Posted on Friday, September 12, 2008 - 03:36 by  from the site ASIC-System On Chip (SoC)-VLSI Design
p style="margin-bottom: 0in; line-height: 150%;"Multiple threshold voltage techniques use both Low Vt and High Vt cells. Use lower threshold gates on critical path while higher threshold gates off the critical path. This methodology improves performance without an increase in power. Flip side of this technique is that Multi Vt cells increase fabrication complexity. It also lengthens the design time.
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Multi Vdd (Voltage)
Posted on Friday, September 12, 2008 - 03:32 by  from the site ASIC-System On Chip (SoC)-VLSI Design
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Multiple Threshold CMOS (MTCMOS) Circuits
Posted on Friday, September 12, 2008 - 03:26 by  from the site ASIC-System On Chip (SoC)-VLSI Design
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Voltage Scaling and DVFS
Posted on Friday, September 12, 2008 - 03:18 by  from the site ASIC-System On Chip (SoC)-VLSI Design
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Power Gating
Posted on Friday, September 12, 2008 - 03:18 by  from the site ASIC-System On Chip (SoC)-VLSI Design
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Low Power Design Techniques
Posted on Tuesday, April 15, 2008 - 02:13 by  from the site ASIC-System On Chip (SoC)-VLSI Design
p style="margin-bottom: 0in;font-family:times new roman;"span style="color: rgb(0, 0, 0);font-size:100%;" span lang="en-GB"Michael Keating et al./span [1] lists several low power techniques to tackle the dynamic and static power consumption in modern SoC designs. Dynamic power control techniques include clock gating, multi voltage, variable frequency, and efficient circuits. Leakage power control techniques include power gating, multi Vt cells.
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