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Posted on  by  from the site Adventures in ASIC Digital Design
Here is an interesting and almost trivial technique for (potential) power reduction, which I never used myself, nor seen used in others’ designs. Well… maybe I am doing the wrong designs… but I thought it is well worth mentioning. So, if any of my readers use this, please do post a short comment on how exactly did you implement it and if it really resulted in some significant savings. We usually have many high activity nets in the design. They are in many cases toggling during calculation more than once per cycle. Even worse, they often drive long and high capacitive nets.
Nir Dahan
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Posted on  by  from the site Adventures in ASIC Digital Design
It is for some reason a common view, that when using replication you also have to pay in increased wire length. It looks reasonable isn’t it? After all, you now have more blocks to wire into and out of and therefore total wire length should increase, right? Well, not really… In some cases this might be true, but in most cases wire length should decrease. Wiring in a chip obeys taxicab geometry laws, so it is a bit less intuitive than usual. Here is a simple example showing how wire length can decrease after replication.
Nir Dahan
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