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Real World Examples #5 – Clock Divider by 5
Posted on Wednesday, August 26, 2009 - 16:28 by Nir Dahan from the site Adventures in ASIC Digital Design
Here is a neat little circuit that was used in an actual project a long, long time ago (in a galaxy far, far away…). The requirement was to build a divide by 5 circuit for the clock with 50% duty cycle. The initial (on reset) behavior was not important – i.e. the circuit could wake up in an undefined state, but should have settled after a given time. The engineer produced the circuit below: Basically, the circuit is made out of a 3-bit counter, that counts from 000 to 100 and then resets. Signal ‘X’ goes high when the value of the counter is either 000, 001 or 010.
Nir Dahan
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Real World Examples #4 - More on “Thinking Hardware”
Posted on Tuesday, January 20, 2009 - 05:10 by Nir Dahan from the site Adventures in ASIC Digital Design
I was reviewing some code not so long ago, and noticed together with the owner of the code, that we had some timing problems. Part of the code looked something like that (Verilog): wire [127:0] a; wire [127:0] b; wire [127:0] c; assign c = select_register ? a : b; For those not familiar with Verilog syntax, the code describes a MUX construct using the ternary operator. The two data inputs for the MUX are “a” and “b” and the select is “select_register”. So why was this code translated into a relatively slow design?
Nir Dahan
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Real World Examples #3 - PRBS Look-ahead
Posted on Friday, August 8, 2008 - 15:02 by Nir Dahan from the site Adventures in ASIC Digital Design
PRBS generation is very useful in many digital design applications as well as in DFT. I am almost always confused when given a PRBS polynomial and asked to implement it, so I find it handy to visit this site. This is all nice and well for simple PRBS patterns. In some systems however, the PHY is working in a much higher rate than the digital core (say n times higher).
Nir Dahan
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