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Net delay

Posted on  by  from the site ASIC-System On Chip (SoC)-VLSI Design
titleNet Delay or Interconnect Delay or Wire Delay or Extrinsic Dela/titlespan style="color: rgb(41, 41, 41);"span style="font-size:130%;"bNet Delay or Interconnect Delay or Wire Delay or Extrinsic Delay or Flight Time/b/span/spanspan style="color: rgb(41, 41, 41);" br / br /Net delay is the difference between the time a signal is first applied to the net and the time it reaches other devices connected to that net. br / br //spanspan style="color: rgb(41, 41, 41);"It is due to the finite resistance and capacitance of the net.
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