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Using vmm_opts to create a configurable environment
Posted on Monday, July 19, 2010 - 12:13 by S. Prashanth from the site Verification Martial Arts
S. Prashanth, Verification & Design Engineer, LSI Logic To accommodate changing specifications and to support different clusters/subsystems which would have multiple processors/memory connected through a bridge), I am building a reusable environment which can support any number of masters and slaves of any standard bus protocols.  The environment requires high level of configurability since it should work for different DUTs.
S. Prashanth
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VMM VIP’s on multiple buses
Posted on Wednesday, May 27, 2009 - 09:09 by Adiel Khan from the site Verification Martial Arts
Adiel Khan, Synopsys CAE Increasingly, more design-oriented engineers are writing VMM code. Some are trying to map typically good design architecture practices to verification development. A dangerous mapping is parameterization, from modules to classes. In my old Verilog testbenches I would develop reusable modules and use #parameters extensively to control the settings of the modules I was instantiating. (It was a sad day when I heard IEEE was deprecating my friend the defparam). 1.
Adiel Khan
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Real World Examples #4 - More on “Thinking Hardware”
Posted on Tuesday, January 20, 2009 - 05:10 by Nir Dahan from the site Adventures in ASIC Digital Design
I was reviewing some code not so long ago, and noticed together with the owner of the code, that we had some timing problems. Part of the code looked something like that (Verilog): wire [127:0] a; wire [127:0] b; wire [127:0] c; assign c = select_register ? a : b; For those not familiar with Verilog syntax, the code describes a MUX construct using the ternary operator. The two data inputs for the MUX are “a” and “b” and the select is “select_register”. So why was this code translated into a relatively slow design?
Nir Dahan
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A Coding Tip for Multi Clock Domain Designs
Posted on Saturday, December 13, 2008 - 15:43 by Nir Dahan from the site Adventures in ASIC Digital Design
Multi clock domain designs are always interesting, but almost always hide some synchronization problems, which are not that trivial. There are tools on the market that identify all(??) clock domain crossings within a design. I personally had no experience with them, so I can’t give an opinion (although I heard some unflattering remarks from fellow engineers). Seems like each company has its own ways of handling this problem. One of the oldest, easiest and IMHO one of the most efficient ways, is to keep strict naming guidelines for your signals, whether combinatorial or sequential !!
Nir Dahan
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Another Reason to Add Hierarchies to Your Designs
Posted on Sunday, November 30, 2008 - 06:35 by Nir Dahan from the site Adventures in ASIC Digital Design
We are usually very annoyed when the team leader insists on code restructuring and hierarchical design. I also know this very well from the other side as well.
Nir Dahan
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Fun With Enable Flip-Flops
Posted on Monday, October 27, 2008 - 16:37 by Nir Dahan from the site Adventures in ASIC Digital Design
Almost each library has enable flip-flops included. Unfortunately, they are not always used to their full potential. We will explore some of their potential in this post. An enable flop is nothing but a regular flop which only registers new data if the enable signal is high, otherwise it keeps the old value. We normally implement this using a MUX and a feedback from the flop’s output as depicted below. So what is the big deal about it? The nice thing is that the enable flop is already implemented by the guys who built the library in a very optimized way.
Nir Dahan
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Why You Don’t See a Lot of Verilog or VHDL on This Site
Posted on Sunday, August 31, 2008 - 14:50 by Nir Dahan from the site Adventures in ASIC Digital Design
I get a lot of emails from readers from all over the world. Many want me to help them with their latest design or problem. This is OK, after all this is what this site is all about - giving tips, tricks and helping other designers making their steps through the complex world of ASIC digital design. Many ask me for solutions directly in Verilog or VHDL. Although this would be pretty simple to give, I try to make sure NOT to do so. The reason is that it is my personal belief that thinking of a design in terms of Verilog or VHDL directly is a mistake and leads to poorer designs.
Nir Dahan
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Sometimes I Repeat Myself
Posted on Saturday, August 30, 2008 - 15:11 by David Robinson from the site Oh, one more thing
"She was mostly immensely relieved to think that virtually everything that anybody had ever told her was wrong" Douglas Adams, "So Long and Thanks for all the Fish" I'm in the process of teaching myself Ruby on Rails at the moment.  There's no great reason for this, other than the fact that I kept hearing people talk about it and curiosity got the better of me.  That's not immediately relevant though.  What is relevant is that in parallel, I'm learning Javascript, and one of the cool new things I learned was this - white space, commenting, and desc
David Robinson
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Size does matter
Posted on Sunday, July 6, 2008 - 12:24 by janick from the site Verification Martial Arts
The VMM Register Abstract Abstraction layer is documented with a 64-bit data value system.
janick
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Dissing this
Posted on Thursday, June 19, 2008 - 03:27 by David Robinson from the site Oh, one more thing
div xmlns="http://www.w3.org/1999/xhtml"pDamn damn damn damn.nbsp; I promised myself that I wouldn't get involved in any more conversations about coding styles - ever, and then Janick has to go and write quot;a title="Permanent Link to Do they diss this “this”?" rel="bookmark" href="http://www.vmmcentral.org/vmartialarts/?p=11"Do they diss this “this”?/aquot;nbsp; Use of quot;this.quot; is a pet hate of mine as it's nothing but a source of annoying bugs.nbsp; Janick has done an excellent job of explaining what quot;this.quot; is for, and why you might want to use it, so I'm just going to be la
David Robinson
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