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Cool Things You Can Do With DVE – Part 3
Posted on Wednesday, April 13, 2011 - 09:00 by yilani from the site Verification Martial Arts
Yaron Ilani, Apps. Consultant, Synopsys If you missed part 1 or part 2 of this series don’t worry, you can go on reading and catch up with the previous parts later on. Today I’m going to show you a small, yet very powerful feature in DVE that you may not be aware of. Remember the last time you had to count clock cycles in the waveform window? Sometimes this is a quick way to verify that an internal counter behaves correctly or that a signal goes up just at the right clock edge. Remember how frustrating it is when you lose count for some reason and have to start over?
yilani
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Cool Things You Can Do With DVE – Part 2
Posted on Thursday, April 7, 2011 - 10:00 by yilani from the site Verification Martial Arts
Yaron Ilani, Apps. Consultant, Synopsys In Part 1 of this series we discussed how SystemVerilog macros might add complexity when it comes to debugging your test bench and how DVE can make your life much easier in that area. Today we’re going to show you another cool feature in DVE that if used wisely, could save you a significant amount of time when debugging. Let’s recall for a moment the two main use models of DVE – Post Processing and Interactive. The former is where you’re debugging your simulation results after it has completed.
yilani
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Cool Things You Can Do With DVE – Part 1
Posted on Sunday, April 3, 2011 - 09:00 by yilani from the site Verification Martial Arts
Yaron Ilani, Apps. Consultant, Synopsys A SystemVerilog test bench could get quite complex. Typical projects today have thousands of lines of code, and the number is constantly on the rise. However, standard base class libraries such as VMM and UVM can help you minimize the amount of code that needs to be rewritten by providing a rich set of macros that substitute long lines of code with a single line. For example, the simple line `vmm_channel(atm_cell) defines a standard VMM channel for an ATM cell with all the necessary fields and methods, all under the hood.
yilani
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Transaction Debugging with Discovery Visualization Environment (DVE) Part-1
Posted on Friday, February 25, 2011 - 20:23 by JL Gray from the site Verification Martial Arts
Asif Jafri, Verilab Inc., Austin, TX The art of verification has evolved dramatically over the last decade. What used to be a very simple verilog testbench which could not possibly cover the vast solution space has evolved into the current monstrosity (Random testbenches) which is a very powerful tool, but the complexity to debug has gone up exponentially.
JL Gray
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Managing VMM Log verbosity in a smart way
Posted on Monday, March 1, 2010 - 22:48 by Srinivasan Venkataramanan from the site Verification Martial Arts
Srinivasan Venkataramanan, CVC Pvt. Ltd. Vishal Namshiker, Brocade Communications India Any complex system requires debugging at some point or the other. To ease the debug process, a good, proven coding practice is to add enough messages for the end user to aid in debug. However as systems become mature the messages tend to become too many and quickly users feel a need for controlling the messages.
Srinivasan Venkataramanan
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Drivers on a Tristate bus….
Posted on Thursday, February 18, 2010 - 17:13 by Srivatsa Vasudevan from the site Verification Martial Arts
Tri-state busses are typically present in a verification environment when we have multiple drivers driving a bus. One of the drivers drives the bus and the rest of the drivers on the bus present high impedance to the bus. By far and large, it is preferred to have a single interface from the testbench side to deal with the tristate bus. This typically helps avoid bus contention. In some circumstances, this may not be easily possible. Why don’t you just imagine having to elaborate a design, run to a certain point and run a drivers() command?
Srivatsa Vasudevan
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Leverage on the built-in callback inside vmm_atomic_gen and be productive with DVE features for VMM debug
Posted on Sunday, February 7, 2010 - 19:14 by srini from the site Verification Martial Arts
Srinivasan Venkataramanan, CVC Pvt. Ltd. Rashmi Talanki, Sasken John Paul Hirudayasamy, Synopsys During a recent Verification environment creation for a customer we had to tap an additional copy/reference of the generated transaction to another component in the environment without affecting the flow. So one producer gets more than one consumer (here 2 consumers). As a first time VMM coder the customer tried using “vmm_channel::peek” on the channel that was connecting GEN to BFM.
srini
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