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Register Abstraction Model with RAL

Posted on  by  from the site Verification Martial Arts
I often get asked how best RAL ought to be used with Designware VIP. Since several of these VIPs provide a mechanism to program registers across different DUTs, I felt it would be useful to create an example with Designware AMBA AHB VIP and RAL.
S. Varun
Posted on  by  from the site Verification Martial Arts
In a verification environment, different components may be trying to access the DUT registers and memories. For example, the BFM might be programming some registers while the bus monitor might be sampling the values of these registers. In specific cases, there may be an interrupt monitor which triggers an Interrupt Service Routine (ISR) whenever it sees an Interrupt pin toggling in the interface. The ISR might end up having to read the Interrupt registers and end up clearing the Interrupt bit/s through a front door access.
Amit Sharma
Posted on  by  from the site Verification Martial Arts
Amit Sharma, Synopsys Usually, designs have a single interface but some designs may have more than one physical interface, each with accessible registers or memories. RAL supports designs with multiple physical interfaces, as well as registers and memories shared across multiple interfaces. In RAL, a physical interface is called a domain. Only blocks and systems can have domains. Domains can contain registers and memories.   Now, how do you enable a register or a memory to be shared across multiple physical interfaces or ‘domains’ in RAL?
Amit Sharma
Posted on  by  from the site Verification Martial Arts
Currently, RAL does not schedule multiple concurrent READ/WRITE accesses to the same register at the same time. RAL assumes all physical transactions to be atomic, i.e. a transaction is completed before the next cycle is started. Even if we try to do a parallel READ, RAL will block one of the two accesses and schedule it sequentially.
S. Varun
Posted on  by  from the site Verification Martial Arts
Amit Sharma, Synopsys In one of my previous posts on  Virtual Registers I talked about how you use RAL to model Virtual Registers or fields which are an efficient means of implementing large number of registers in  memory or RAM instead of individual flip-flops.  I also mentioned that they are  implemented as arrays associated with a memory. In this post, I will talk about how you access these registers through RAL. Normal registers can be accessed using  the hierarchical name in RAL.
Amit Sharma
Posted on  by  from the site Verification Martial Arts
Amit Sharma, Synopsys Typically, fields and registers are assumed to be implemented in individual, dedicated hardware structures with a constant and permanent physical location such as a set of D flip-flops.
Amit Sharma
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