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Moore's Law

Posted on  by  from the site harry ... the ASIC guy
(Part 4 in the series Which Direction for EDA? 2D, 3D, or 360?) In the last 2 posts in this series, I examined the lithography and transistor design issues that will need to be solved in order to save 2D scaling as we know it. In this post I will look at several other considerations. For the moment, let’s assume that we are able to address the lithography and transistor design issues that I’ve identified in the previous posts.
harry
Posted on  by  from the site harry ... the ASIC guy
 (Part 3 in the series Which Direction For EDA: 2D,3D, or 360?) In the last blog post, I started to examine the question “is 2D scaling really dead or just mostly dead?” I looked at the most challenging issue for 2D scaling, lithography. But even if we can draw the device patterns somehow on the wafer at smaller and smaller geometries, does not necessarily mean that the circuits will deliver the performance (speed, area, power) improvements that Moore’s Law has delivered in the past.
harry
Posted on  by  from the site harry ... the ASIC guy
A hiker comes to a fork in the road and doesn’t know which way to go to reach his destination. Two men are at the fork, one of whom always tells the truth while the other always lies. The hiker doesn’t know which is which. He may ask one of the men only one question to find his way. Which man does he ask, and what is the question? __________ There’s been lots of discussion over the last month or 2 about the direction of EDA going forward. And I mean literally, the “direction” of EDA.
harry
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