EDA

Although I had heard his name mentioned quite often, it wasn’t until this year at DAC that I finally met Scott Clark  for the first time. Scott was describing how, as Director of Engineering Infrastructure at Broadcom, he led a project to virtualize Broadcom’s internal data center in order to transform it into a private cloud. It was a great discussion.

 (Part 3 in the series Which Direction For EDA: 2D,3D, or 360?) In the last blog post, I started to examine the question “is 2D scaling really dead or just mostly dead?” I looked at the most challenging issue for 2D scaling, lithography. But even if we can draw the device patterns somehow on the wafer at smaller and smaller geometries, does not necessarily mean that the circuits will deliver the performance (speed, area, power) improvements that Moore’s Law has delivered in the past.

(Photo courtesy Ron Ploof)  I had the pleasure yesterday of interviewing Brian Bailey in the Synopsys Conversation Central Stage at DAC. We discussed his roots in verification working with the initial developers of digital simulation tools and his blogging experiences these past few years. There are, of course, even a few comments on the difference between journalists and bloggers You can listen to this half hour interview at the Synopsys Blog Talk Radio site. I’d be interested in your comments on the show and the format as well.

A friend asked me what I thought about Oasys’ announcement last week that Juniper Networks was now a customer of theirs. I’ll admit that I was lukewarm. On the one hand, a large high-end networking chip is exactly the sweet spot for a fast synthesis tool. On the other hand, it did not change the fact that the number of these large designs is dwindling and that the industry is looking more towards the front-end of the design cycle than the back. So, today he asked me what I thought about Oasys’ announcement of it’s partnership with Xilinx. Now this was interesting.