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Which Direction for EDA - 2D, 3D, or 360?
Posted on Sunday, May 23, 2010 - 23:46 by harry from the site harry ... the ASIC guy
A hiker comes to a fork in the road and doesn’t know which way to go to reach his destination. Two men are at the fork, one of whom always tells the truth while the other always lies. The hiker doesn’t know which is which. He may ask one of the men only one question to find his way. Which man does he ask, and what is the question? __________ There’s been lots of discussion over the last month or 2 about the direction of EDA going forward. And I mean literally, the “direction” of EDA.
harry
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The Burning Platform
Posted on Tuesday, March 2, 2010 - 01:26 by harry from the site harry ... the ASIC guy
Although I was unable to attend DVCon last week, and I missed the Jim Hogan and Paul McLellan presenting “So you want to start an EDA Company? Here’s how“, I was at least able to sit in on an interesting webinar offered by RTM Consulting entitled Achieving Breakthrough Customer Satisfaction through Project Excellence. As you may recall, I wrote a previous blog post about a Consulting Soft Skills training curriculum developed by RTM in conjunction with Mentor Graphics for their consulting organization.
harry
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My Obligatory TOP 10 for 2009
Posted on Thursday, December 31, 2009 - 15:50 by harry from the site harry ... the ASIC guy
http://www.flickr.com/photos/optical_illusion/ / CC BY 2.0 What’s a blog without some sort of obligatory year end TOP 10 list? So, without further ado, here is my list of the TOP 10 events, happenings, occurrences, observations that I will remember from 2009. This is my list, from my perspective, of what I will remember.
harry
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An ASIC Guy Visits An FPGA World - Part II
Posted on Monday, June 22, 2009 - 02:07 by harry from the site harry ... the ASIC guy
I mentioned a few weeks ago that I am wrapping up a project with one of my clients and beating the bushes for another project to take its place. As part of my search, I visited a former colleague who works at a small company in Southern California. This company designs a variety of products that utilize FPGAs exclusively (no ASICs), so I got a chance to understand a little bit more about the differences between ASIC and FPGA design.
harry
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An ASIC Guy Visits An FPGA World
Posted on Thursday, June 4, 2009 - 02:49 by harry from the site harry ... the ASIC guy
I hear so often nowadays that FPGAs are the new ASICs. So I decided to take off half a day and attend a Synopsys FPGA Seminar just down the street from where I’m working (literally a 5 minute walk). I would like to share some observations as an ASIC guy amongst FPGA guys and gals. Observation #1 - FPGA people put their pants on one leg at a time, just like me. (Actually, I sometimes do both legs at the same time, but that’s another story).
harry
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FPGA Implementation of FIR Filter
Posted on Thursday, September 11, 2008 - 02:05 by  from the site ASIC-System On Chip (SoC)-VLSI Design
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New Asynchronous FIFO Design
Posted on Tuesday, January 1, 2008 - 05:36 by  from the site ASIC-System On Chip (SoC)-VLSI Design
div style="text-align: left;"b style=""span style="line-height: 150%;font-size:14;" span style="font-size:130%;"Asynchronous FIFO - General Workingbr //spano:p/o:p/span/bbr /a style="color: rgb(51, 102, 255);" href="http://asic-soc.blogspot.com/2007/12/verilog-code-for-asynchronous-fifo.html"Verilog code for Asynchronous FIFO /aand its a style="color: rgb(51, 102, 255);" href="http://asic-soc.blogspot.com/2007/12/verilog-test-bench-for-asynchronous.html"verilog test bench code/a are already given in previous posts.br /br /Let us have a small recap of asynchronous FIFO working and then we will
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Asynchronous FIFO: Simulation and Synthesis
Posted on Tuesday, January 1, 2008 - 05:30 by  from the site ASIC-System On Chip (SoC)-VLSI Design
span style="font-size:130%;"o:p/o:pbr //spanp class="MsoNormal" style="text-align: justify; line-height: 150%;"span style="font-size:130%;"b style=""span style="line-height: 150%;"Asynchronous FIFO: Simulation using Modelsimo:p/o:p/span/b/span/p p class="MsoNormal" style="text-align: justify; line-height: 150%;"o:pspan style="font-size:85%;" Note: Diagram numbers are continued from thespan style="color: rgb(51, 51, 255);" /spana style="color: rgb(51, 51, 255);" href="http://asic-soc.blogspot.com/2007/12/new-asynchronous-fifo-design.html"previous post/aspan style="color: rgb(51, 51, 255);"./s
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Asynchronous FIFO-Clock Generation Using DCM
Posted on Tuesday, January 1, 2008 - 05:12 by  from the site ASIC-System On Chip (SoC)-VLSI Design
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