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Intel

Posted on  by  from the site harry ... the ASIC guy
(Part 4 in the series Which Direction for EDA? 2D, 3D, or 360?) In the last 2 posts in this series, I examined the lithography and transistor design issues that will need to be solved in order to save 2D scaling as we know it. In this post I will look at several other considerations. For the moment, let’s assume that we are able to address the lithography and transistor design issues that I’ve identified in the previous posts.
harry
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