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An ASIC Guy Visits An FPGA World - Part II
Posted on Monday, June 22, 2009 - 02:07 by harry from the site harry ... the ASIC guy
I mentioned a few weeks ago that I am wrapping up a project with one of my clients and beating the bushes for another project to take its place. As part of my search, I visited a former colleague who works at a small company in Southern California. This company designs a variety of products that utilize FPGAs exclusively (no ASICs), so I got a chance to understand a little bit more about the differences between ASIC and FPGA design.
harry
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Setting The Record Straight
Posted on Thursday, February 19, 2009 - 02:50 by harry from the site harry ... the ASIC guy
Since conducting the Verification Methodology Poll and publishing the raw results last week, I’ve been planning to follow up with a post that digs a little deeper into the numbers. Things have gotten rather busy in the meantime, both at work and with organizing the SaaS and Cloud Computing EDA Roundtable for next week at DVCon. So I’ve let it slip a little. Well, I noticed today that the verification methodology poll was referenced in a Cadence blog post by Adam Sherer.
harry
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Verification Methodology Poll Results
Posted on Wednesday, February 11, 2009 - 10:35 by harry from the site harry ... the ASIC guy
Last week I initiated a poll of verification methodologies being used for functional verification of ASICs. Unlike other polls or surveys, this one was done in a very “open” fashion using a website that allows everyone to view the raw data. In this way, anyone can analyze the data and draw the conclusions that make sense to them, and those conclusions can be challenged and debated based on the data. What happened next was interesting. Within 48 hours, the poll had received almost 200 responses from all over the world.
harry
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Quick Update On Verification Methodology Poll
Posted on Friday, February 6, 2009 - 03:03 by harry from the site harry ... the ASIC guy
Quick update for everyone… Regarding the Verification Methodology Poll I started the other day, I was able to go through the log files and identify the obvious malicious activity.  There was a string of deletes and changes of VMM votes to OVM/e votes. Then a string of deletes of OVM votes. I’m going to add back the original entries to make the data whole again. In the meantime, the obvious malicious activity has subsided, and now there is only a trickle of clearly valid votes coming in.
harry
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Verification Methodology Poll
Posted on Tuesday, February 3, 2009 - 03:41 by harry from the site harry ... the ASIC guy
In response to a recent post regarding the verification survey on the DVCon website, Jeremy Ralph of PDTi expressed that he’d “be interested to know what proportion of the SV is OVM vs. VMM”, a question that was missing from the survey. Considering the whole kerfuffle concerning OVM and VMM over the last year, I thought this would be a good question for you, the ones really using the tools. I also thought it would be a good opportunity to try out this new Doodle survey tool I was told about. So … I created the first ASIC guy survey on Doodle.
harry
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VMM on Questa & IUS Redux? Anything New Here?
Posted on Friday, December 5, 2008 - 14:40 by harry from the site harry ... the ASIC guy
Considering what I’ve been hearing about the status of the Accellera VIP Subcommitee activity regarding OVM / VMM integration, I was rather surprised to see the following synchronized press releases from Mentor and Cadence yesterday: Mentor Solution for OVM Reuse of Legacy VMM Code Cadence Open Source OVM Adoption for VMM Users As I understand, the Accellera VIP Subcommittee has just recently begun tackling the real crux issues regarding integrating the 2 methodologies such as: Casting of disparate types Synchronization of the simulation phases Message reporting My speculation is t
harry
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Leverage Can Be Your Friend
Posted on Monday, September 29, 2008 - 11:24 by harry from the site harry ... the ASIC guy
During these last few weeks of the subprime mortgage crisis in the US, many of us have become all too familiar with the term “leverage” as it applies to those entities that used to be called investment banks.  That kind of leverage is very powerful and is also very dangerous, as we all found out. There is a 2nd type of leverage that we engineers learned about in basic physics.
harry
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Birth of an EDA Revolution
Posted on Friday, September 5, 2008 - 14:56 by harry from the site harry ... the ASIC guy
I can’t sleep at night. This Idea has been bouncing around in my head for the past few months. I can’t shake it. If you know me, then you’ve probably heard me talk about the Idea or ask your opinion about the Idea or whether I’m crazy. I’ve been itching to blog about this Idea, but haven’t been able to figure out the right way to approach it. Then, the other day, Ron Ploof gave me a way to approach the Idea in my blog. Please read Ron’s post on the Birth of a New Media Revolution first before continuing.
harry
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Are *you* confused?
Posted on Wednesday, August 13, 2008 - 08:21 by David Robinson from the site Oh, one more thing
While sipping on my revive-me-from-the-dead coffee this morning, I had a scan of JL's latest post on the ongoing VMM/OVM spat.  This pointed me at an article by Richard Goering in SCDSource which had the following:Bartleson said, however, that Synopsys has no intent to support OVM. "Our goal is to support the Accellera [VIP] standard, so we get some unification.
David Robinson
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