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Real World Examples #4 - More on “Thinking Hardware”
Posted on Tuesday, January 20, 2009 - 05:10 by Nir Dahan from the site Adventures in ASIC Digital Design
I was reviewing some code not so long ago, and noticed together with the owner of the code, that we had some timing problems. Part of the code looked something like that (Verilog): wire [127:0] a; wire [127:0] b; wire [127:0] c; assign c = select_register ? a : b; For those not familiar with Verilog syntax, the code describes a MUX construct using the ternary operator. The two data inputs for the MUX are “a” and “b” and the select is “select_register”. So why was this code translated into a relatively slow design?
Nir Dahan
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Who Said Clock Skew is Only Bad?
Posted on Thursday, October 2, 2008 - 08:35 by Nir Dahan from the site Adventures in ASIC Digital Design
We always have this fear of adding clock skew. Well, seems like this is one of the holy cows of digital design, but sometimes clock skew can be advantageous. Take a look at the example below. The capturing flop would normally violate setup requirements due to the deep logic cloud. By intentionally adding delay we could help make the clock arrive later and thus meet the setup condition. Nothing comes for free though, if we have another register just after the capturing one, the timing budget there will be cut. This technique can also be implemented on the block level as well.
Nir Dahan
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Max Area = 0 ?
Posted on Sunday, August 24, 2008 - 15:38 by Nir Dahan from the site Adventures in ASIC Digital Design
You are working on a design, you simulated the thing and it looks promising, first synthesis run also looks clean - jobs done right? wrong! Many ASIC designers do not care for the area of their blocks. It has to meet the max_transition, max_capacitance and timing requirements but who cares about the area? Well if you are an engineer in soul, you should care. I completely agree that it is a well accepted strategy not to constrain for area (or max_area = 0) when you first approach synthesis.
Nir Dahan
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