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Managing VMM Log verbosity in a smart way
Posted on Monday, March 1, 2010 - 22:48 by Srinivasan Venkataramanan from the site Verification Martial Arts
Srinivasan Venkataramanan, CVC Pvt. Ltd. Vishal Namshiker, Brocade Communications India Any complex system requires debugging at some point or the other. To ease the debug process, a good, proven coding practice is to add enough messages for the end user to aid in debug. However as systems become mature the messages tend to become too many and quickly users feel a need for controlling the messages.
Srinivasan Venkataramanan
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Connecting Multiple Analysis Ports to a Single Analysis Export
Posted on Tuesday, February 9, 2010 - 10:24 by JL Gray from the site Verification Martial Arts
Today’s post was written by my colleague Asif Jafri. Enjoy! JL by Asif Jafri Asif Jafri is a verification engineer at Verilab. This post introduces the VMM implementation of the Transaction Level Modeling (TLM) 2.0 specification of how you can connect multiple broadcasting ports to the same receiving export using peer ID’s. Figure 1 shows multiple initiators communicating with the same target. The initiators can be monitors on either side of your DUT passing transaction to a single scoreboard which keeps track of the transactions and does various checks.
JL Gray
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Leverage on the built-in callback inside vmm_atomic_gen and be productive with DVE features for VMM debug
Posted on Sunday, February 7, 2010 - 19:14 by srini from the site Verification Martial Arts
Srinivasan Venkataramanan, CVC Pvt. Ltd. Rashmi Talanki, Sasken John Paul Hirudayasamy, Synopsys During a recent Verification environment creation for a customer we had to tap an additional copy/reference of the generated transaction to another component in the environment without affecting the flow. So one producer gets more than one consumer (here 2 consumers). As a first time VMM coder the customer tried using “vmm_channel::peek” on the channel that was connecting GEN to BFM.
srini
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Just in time for the holidays: VMM 1.2!
Posted on Tuesday, December 15, 2009 - 07:26 by Janick Bergeron from the site Verification Martial Arts
Janick Bergeron Synopsys Fellow I am pleased to see that the OpenSource version of VMM 1.2 is finally released. It is the culmination of six months of hard work by the entire VMM teams and the hundreds of customers who have provided inputs on its requirements and the dozens of teams who have contributed their feedback during the beta period. What is new in VMM 1.2 is a “secret de Polichinelle“. Ever since the start of the beta period, several VMM users and Synopsys engineers have published tutorials, seminar presentations and blog articles on many of its powerful aspects.
Janick Bergeron
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class factory
Posted on Wednesday, August 26, 2009 - 01:46 by Wei-Hua Han from the site Verification Martial Arts
  Weihua Han, CAE, Synopsys As a well-known Object-Oriented technique, class factory has actually been applied in VMM since inception. For instance, in the vmm atomic and scenario generators, by assigning different blueprints to randomized_obj and scenario_set[] properties, these generators can generate transactions with user specified patterns. Using the class factory pattern, users create an instance with a pre-defined method (such as allocate() or copy()) instead of the constructor.
Wei-Hua Han
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Introducing VMM 1.2
Posted on Monday, July 27, 2009 - 03:41 by Fabian Delguste from the site Verification Martial Arts
Fabian Delguste / Synopsys Verification Group I’m very pleased to announce that VMM 1.2 beta is now available. You’re welcome to enroll our VMM 1.2 Beta program by signing up the form on VMM Central at: http://www.vmmcentral.org/cgi-bin/beta/reg1.cgi As you know, the VMM methodology defines industry best practices for creating robust, reusable and scalable verification environments using SystemVerilog.
Fabian Delguste
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An ASIC Guy Visits An FPGA World - Part II
Posted on Monday, June 22, 2009 - 02:07 by harry from the site harry ... the ASIC guy
I mentioned a few weeks ago that I am wrapping up a project with one of my clients and beating the bushes for another project to take its place. As part of my search, I visited a former colleague who works at a small company in Southern California. This company designs a variety of products that utilize FPGAs exclusively (no ASICs), so I got a chance to understand a little bit more about the differences between ASIC and FPGA design.
harry
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A generic functional coverage solution based on vmm_notify
Posted on Monday, June 15, 2009 - 03:05 by Wei-Hua Han from the site Verification Martial Arts
Weihua Han, CAE, Synopsys Functional coverage plays an essential role in Coverage Driven Verification. In this blog, I’ll explain a modular way of modeling and implementing  functional coverage models. SystemVerilog users can take the advantage of  the “covergroup” construct to implement functional coverage. However this is not enough.
Wei-Hua Han
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VMM VIP’s on multiple buses
Posted on Wednesday, May 27, 2009 - 09:09 by Adiel Khan from the site Verification Martial Arts
Adiel Khan, Synopsys CAE Increasingly, more design-oriented engineers are writing VMM code. Some are trying to map typically good design architecture practices to verification development. A dangerous mapping is parameterization, from modules to classes. In my old Verilog testbenches I would develop reusable modules and use #parameters extensively to control the settings of the modules I was instantiating. (It was a sad day when I heard IEEE was deprecating my friend the defparam). 1.
Adiel Khan
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The hidden pitfalls of type name hiding in a derived class
Posted on Saturday, May 9, 2009 - 02:18 by Wei-Hua Han from the site Verification Martial Arts
Weihua Han, CAE, Synopsys Here I describe one major difference between virtual and non-virtual methods, and how type name hiding can collide with these methods. This is commonly used OOP feature in SystemVerilog. “type name hiding” here refers to the situation where a user type definition in the derived class uses the same type name defined in base class, i.e, the new type definition in derived class “hides” the type definition in base class.
Wei-Hua Han
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