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Cool Things You Can Do With DVE – Part 1
Posted on Sunday, April 3, 2011 - 09:00 by yilani from the site Verification Martial Arts
Yaron Ilani, Apps. Consultant, Synopsys A SystemVerilog test bench could get quite complex. Typical projects today have thousands of lines of code, and the number is constantly on the rise. However, standard base class libraries such as VMM and UVM can help you minimize the amount of code that needs to be rewritten by providing a rich set of macros that substitute long lines of code with a single line. For example, the simple line `vmm_channel(atm_cell) defines a standard VMM channel for an ATM cell with all the necessary fields and methods, all under the hood.
yilani
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Blocking and Non-blocking Communication Using the TLI
Posted on Thursday, March 31, 2011 - 10:36 by John Aynsley from the site Verification Martial Arts
John Aynsley, CTO, Doulos In the previous blog post I introduced the VCS TLI Adapters for transaction-level communication between SystemVerilog and SystemC. Now let’s look at the various coding styles supported by the TLI Adapters, and at the same time review the various communication options available in VMM 1.2. We will start with the options for sending transactions from SystemVerilog to SystemC. VMM 1.2 allows transactions to be sent through the classic VMM channel or through the new-style TLM ports, which come in blocking- and non-blocking flavors.
John Aynsley
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Generating microcode stimuli using a constrained-random verification approach
Posted on Thursday, July 15, 2010 - 13:16 by Shankar Hemmady from the site Verification Martial Arts
As microprocessor designs have grown considerably in complexity, generating microcode stimuli has become increasingly challenging.  An article by AMD and Synopsys engineers in EE Times explores using a hierarchical constrained-random approach to accelerate generation and reduce memory consumption, while providing optimal distribution and biasing to hit corner cases using the Synopsys VCS constraint solver. You can find the full article in PDF here.
Shankar Hemmady
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UVM-EA Release Details
Posted on Thursday, May 20, 2010 - 21:30 by JL Gray from the site Cool Verification
As I mentioned earlier in the week, the Universal Verification Methodology – Early Adopter release (UVM-EA) was announced on Monday and can be downloaded from the Accellera website. The process for putting together this release has been both exhilarating and...
JL Gray
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UVM-EA Release Now Available
Posted on Monday, May 17, 2010 - 10:28 by JL Gray from the site Cool Verification
Just a quick note - the Universal Verification Methodology Early Adopter (UVM-EA) release is now available on the Accellera website. I'll post additional details on what the release includes later today.
JL Gray
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Video: UVM Register Package Survey Results
Posted on Wednesday, May 5, 2010 - 17:49 by JL Gray from the site Cool Verification
I gave a presentation earlier today on the UVM register package survey results. I decided to record a video of the presentation for your viewing pleasure. One thing I didn't address in the video is a question I've received a...
JL Gray
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Warning: The UVM "Early Adopter" (UVM-EA) release does not exist yet!
Posted on Sunday, April 11, 2010 - 22:20 by JL Gray from the site Cool Verification
Some of you may have seen an announcement on Friday describing an early adopter kit of the UVM "based on the Accellera Verification IP Technical Subcommittee (VIP-TSC) decisions to date". Being a member of the Accellera VIP-TSC myself, I can...
JL Gray
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Register Packages and the UVM
Posted on Tuesday, March 9, 2010 - 22:32 by JL Gray from the site Cool Verification
Many of the Accellera VIP TSC members are in Marlborough, MA this week discussing what features should be part of the first release of the new UVM (Unified Verification Methodology). For those of you who are not familiar, the UVM...
JL Gray
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Motivation for the UVM
Posted on Tuesday, February 16, 2010 - 23:24 by JL Gray from the site Cool Verification
In the beginning, there was SystemVerilog, and it was good. Through it some testbenches were made; without it other testbenches were made. In SystemVerilog was light, but also darkness in the form of a set of missing features that had...
JL Gray
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SystemVerilog 2012, DVCon 2010, and Travel
Posted on Monday, January 25, 2010 - 00:37 by JL Gray from the site Cool Verification
Now that the SystemVerilog 2009 standard has been released, the P1800 working group is getting ready to start work on the next version of the SystemVerilog standard. As part of that effort, they are soliciting feedback in preparation for an...
JL Gray
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